摘 要(Abstract):
With the dimension scaling in dimension, the transistor gate controllability becomes weaker owing to the pronounced source-drain tunneling. Hence, the transistor body thickness needs to be reduced to ensure efficient electrostatic control. New materials such as “ultra-thin” 2D semiconducting materials have attracted attention. In this talk, I would like to provide analysis and arguments on the possibility to scale the device dimension, for example down to 1nm technology node or beyond, using 2D transition metal dichalcogenides (TMD) semiconductors. The benchmark of 2D semiconductors and Si at various technology nodes shall also be briefed.
There are many challenges on device fabrication. Here, I would like to discuss on several major bottlenecks and the advancements we and collaborators have achieved recently. (1) We discover that hydroxide vapor phase epitaxy enables the growth of WS2 monolayers with a significantly lower density of structural defects, which make the electron mobility peaked at ~ 200 cm2/Vs. (2) The mechanism of wafer-scale growth of 2D materials will also be discussed. (3) Ultrahigh-k dielectrics can be applied onto short-channel (<30 nm) 2D monolayer transistors to greatly lower the subthreshold swing (down to 70 mV dec-1) with an ON/OFF current ratio up to 107. (4) Semimetal is a feasible n-type contact metal to TMD monolayers that can achieve almost zero SB height. Many other unresolved challenges shall also be discussed.
演講語言 (Language): in English
接待人 (Host): 邱雅萍(Chiu, Ya-Ping) 博士